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september 2008 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 FSFA2100 ? fairchild power switch (fps ? ) for half-bridge pwm converter FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converters features ? optimized for complementary driven half-bridge soft-switching converters ? can be applied to various topologies: asymmetric pwm half-bridge converters, asymmetric pwm flyback converters, asymmetric pwm forward converters, active clamp flyback converters ? high efficiency through zero-voltage-switching (zvs) ? internal superfet?s with fast-recovery type body diode (t rr =120ns) ? fixed dead time (200ns) optimized for mosfets ? up to 300khz operating frequency ? internal soft-start ? pulse-by-pulse current limit ? burst-mode operation for low standby power consumption ? protection functions: over-voltage protection (ovp), over-load protection (olp), abnormal over-current protection (aocp), internal thermal shutdown (tsd) applications ? pdp and lcd tvs ? desktop pcs and servers ? adapters ? telecom power supplies description the growing demand for higher power density and low profile in power converter designs has forced designers to increase switching frequencie s. operation at higher frequencies considerably reduces the size of passive components, such as transform ers and filters. however, switching losses have been an obstacle to high- frequency operation. to reduce switching losses and allow high-frequency operation, pulse width modulation (pwm) with soft-switching techniques have been developed. these techniques allow switching devices to be softly commutated, which dramatically reduces the switching losses and noise. FSFA2100 is an integrated pwm controller and superfet? specifically designed for zero-voltage- switching (zvs) half-bridge converters with minimal external components. the internal controller includes an oscillator, under-voltage-lockout, leading-edge blanking (leb), optimized high-side and low-side gate driver, internal soft-start, temper ature-compensated precise current sources for loop compensation and self- protection circuitry. compared with discrete mosfet and pwm controller solution, FSFA2100 can reduce total cost; component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. ordering information part number operating junction temperature r ds(on_max) maximum output power without heatsink (v in =350~400v) (1,2) maximum output power with heatsink (v in =350~400v) (1,2) package eco status FSFA2100 -40 to +130c 0.38 200w 450w 9-sip rohs notes: 1. the junction temperature can limit the maximum output power. 2. maximum practical continuous power in an open-frame design at 50 c ambient. for fairchild?s definition of ?green? eco status, please visit: http://www.fairchildsemi.com/com pany/green/rohs_green.html .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 2 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter application circuit diagram r sense control ic c dl v cc v dl lvcc r t v fb cs sg pg v ctr hvcc c b l lk lm ns v o d1 d2 r f c f np ns ka431 v in figure 1. typical application circuit for an asymmetric pwm half-bridge converter r sense control ic c dl v cc v dl lvcc r t v fb cs sg pg v ctr hvcc c b l lk lm v o d1 r f c f np ns ka431 v in figure 2. typical application circuit for an asymmetric pwm flyback converter
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 3 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter block diagram figure 3. internal block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 4 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter pin configuration 1 2 3 4 5 6 7 8 9 10 v dl v fb r t cs sg pg lvcc hvcc v ctr figure 4. package diagram pin definitions pin # name description 1 v dl this is the drain of the high-side mosfet, typically connected to the input dc link voltage. 2 v fb this pin is connected to the inverting input of the pwm comparator internally and to the opto-coupler externally. the duty cycle is determined by the voltage on this pin. 3 r t this pin programs the switching frequency using a resistor. 4 cs this pin senses the current flowing through the low-side mosfet. typically, negative voltage is applied on this pin. 5 sg this pin is the control ground. 6 pg this pin is the power ground. this pin is connected to the source of the low-side mosfet. 7 lv cc this pin is the supply voltage of the control ic. 8 nc no connection. 9 hv cc this is the supply voltage of the high-side gate-drive circuit ic. 10 v ctr this is the drain of the low-side mosfet. typi cally, a transformer is connected to this pin.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 5 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing t he parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a =25 c unless otherwise specified. symbol parameter min. max. unit v ds maximum drain-to-source voltage (v dl -v ctr and v ctr-pg ) 600 v lv cc low-side supply voltage -0.3 25.0 v hv cc to v ctr high-side v cc pin to low-side drain voltage -0.3 25.0 v hv cc high-side floating supply voltage -0.3 625.0 v v fb feedback pin input voltage -0.3 lv cc v v cs current sense (cs) pin input voltage -5.0 1.0 v v rt r t pin input voltage -0.3 5.0 v dv ctr /dt allowable low-side mosfet drain voltage slew rate 50 v/ns p d total power dissipation (3) 12.0 w maximum junction temperature (4) +150 t j recommended operating junction temperature (4) -40 +130 c t stg storage temperature range -55 +150 c mosfet section v dgr drain gate voltage (r gs =1m ) 600 v v gs gate source (gnd) voltage 30 v i dm drain current pulsed 33 a t c =25 c 11 i d continuous drain current t c =100 c 7 a package section torque recommended screw torque 5~7 kgfcm notes: 3. per mosfet when both mosfets are conducting. 4. the maximum value of the recommended operating junc tion temperature is limited by thermal shutdown. thermal impedance t a =25 c unless otherwise specified. symbol parameter value unit jc junction-to-case center thermal impedanc e (both mosfets conducting) 10.44 oc/w
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 6 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter electrical characteristics t a =25 c and lv cc =17v unless otherwise specified. symbol parameter test conditions min. typ. max. unit mosfet section i d =200 a, t a =25 c 600 bv dss drain-to-source breakdown voltage i d =200 a, t a =125 c 650 v r ds(on) on-state resistance v gs =10v, i d =5.5a 0.32 0.38 t rr body diode reverse recovery time (5) v gs =0v, i diode =11.0a, di diode /dt=100a/ s 120 ns supply section i lk offset supply leakage current hv cc =v ctr =600v 50 a i q hv cc quiescent hv cc supply current (hv cc uv+) - 0.1v 50 120 a i q lv cc quiescent lv cc supply current (lv cc uv+) - 0.1v 100 200 a f osc =100khz, v fb > 3v hv cc =17v 6 9 ma i o hv cc operating hv cc supply current (rms value) no switching, v fb < 1v hv cc =17v 100 200 a f osc =100khz, v fb > 3v 7 11 ma i o lv cc operating lv cc supply current (rms value) no switching, v fb < 1v 2 4 ma uvlo section lv cc uv+ lv cc supply under-voltage positive going threshold (lv cc start) 13.0 14.5 16.0 v lv cc uv- lv cc supply under-voltage negative going threshold (lv cc stop) 10.2 11.3 12.4 v lv cc uvh lv cc supply under-voltage hysteresis 3.2 v hv cc uv+ hv cc supply under-voltage positive going threshold (hv cc start) 8.2 9.2 10.2 v hv cc uv- hv cc supply under-voltage negative going threshold (hv cc stop) 7.8 8.7 9.6 v hv cc uvh hv cc supply under-voltage hysteresis 0.5 v oscillator and feedback section v rt v-i converter threshold voltage 1.5 2.0 2.5 v f osc output oscillation frequency r t =27k 94 100 106 khz d max maximum duty cycle v fb =4v 45 50 55 % d min minimum duty cycle v fb =0v 0 % v fb max maximum feedback voltage for d max d max 48% 2.7 3.0 3.3 v i fb feedback source current v fb =0v 370 470 570 a v bh burst mode high-threshold voltage 1.34 1.50 1.66 v v bl burst mode low-threshold voltage 1.16 1.30 1.44 v v bhy burst mode hysteresis voltage 0.1 0.2 0.3 v t ss internal soft-start time f osc =100khz 10 15 20 ms continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 7 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter electrical characteristics (continued) t a =25 c and lv cc =17v unless otherwise specified. symbol parameter test conditions min. typ. max. unit protection section i olp olp delay current v fb =5v 3.8 5.0 6.2 a v olp olp protection voltage v fb > 6v 6.3 7.0 7.7 v v ovp lv cc over-voltage protection lv cc > 21v 21 23 25 v v aocp aocp threshold voltage v/ t=-1v/s -1.0 -0.9 -0.8 v t bao aocp blanking time (5) v cs < v aocp ; v/ t=-1v/s 50 ns t da delay time (low-side) from v aocp to switch off (5) v/ t=-1v/s 250 400 ns v lim pulse-by-pulse current limit threshold voltage v/ t=-0.1v/s -0.64 -0.58 -0.52 v t bl pulse-by-pulse current limit blanking time v cs < v lim ; v/ t=-0.1v/s 150 ns t dl delay time (low-side) from v lim to switch off (5) v/ t=-0.1v/s 450 ns t sd thermal shutdown temperature (5) 110 130 150 c i su protection latch sustain lv cc supply current lv cc =7.5v 100 150 a v prset protection latch reset lv cc supply voltage 5 v dead-time control section d t dead time (6) 200 ns notes: 5. this parameter, although guaranteed, is not tested in production. 6. these parameters, although guaranteed, are te sted only in eds (wafer test) process.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 8 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter typical performance characteristics these characteristic graphs are normalized at t a =25oc. 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 5. maximum duty cycle vs. temperature figure 6. switching fre quency vs. temperature 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 7. high-side v cc (hv cc ) start vs. temperature figure 8. high-side v cc (hv cc ) stop vs. temperature 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 9. low-side v cc (lv cc ) start vs. temperature figure 10. low-side v cc (lv cc ) stop vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 9 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter typical performance characteristics (continued) these characteristic graphs are normalized at t a =25oc. 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 11. olp delay current vs. temperature figure 12. olp voltage vs. temperature 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 13. lv cc ovp voltage vs. temperature figure 14. r t voltage vs. temperature 0.9 0.95 1 1.05 1.1 -40 -20 0 25 50 75 100 temp ( ) normalized at 25 0.9 0.95 1 1.05 1.1 -40-200 255075100 temp ( ) normalized at 25 figure 15. v bh voltage vs. temperature figure 16. v lim voltage vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 10 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter functional description 1. internal oscillator : FSFA2100 employs a current- controlled oscillator as shown in figure 17. internally, the voltage of the r t pin is regulated at 2v and the charging/discharging current for the oscillator capacitor c t is determined by the current flowing out of the r t pin (i ctc ). when the r t pin is pulled down to the ground with a resistor r set , the switching frequency is fixed as: ) ( 100 27 khz r k f set s = (1) figure 17. current controlled oscillator 2. pwm control : figure 18 shows the typical control circuit configuration. the opto-coupler transistor should be connected to the v fb pin in parallel with the feedback capacitor to control the duty cycle. figure 18. pwm cont rol configuration figure 19 shows the internal block diagram for pwm operation. duty cycle is controlled by comparing the feedback voltage to the triangular signal with a range from 1v to 3v. figure 19. internal pwm block diagram 3. protection circuits : the FSFA2100 has overload protection (olp), abnormal over-current protection (aocp), over-voltage protection (ovp), and thermal shutdown (tsd) self-protective functions. the olp and ovp are auto-restart mode protections, while the aocp and tsd are latch-mode protections, as shown in figure 20. auto-restart mode protection: once the fault condition is detected, the switching is terminated and the mosfets remain off. when lv cc falls down to lv cc stop voltage of around 11v, the protection is reset. the fps resumes normal operation when lv cc reaches the start voltage of about 14v. latch-mode protection: once this protection is triggered, the switching is terminated and the mosfets remain off. the latch is reset only when lv cc is discharged below 5v. figure 20. protection blocks low-side mosfet current should be sensed for pulse- by-pulse current limit and aocp. the FSFA2100 senses drain current as a negative voltage, as shown in figure 21 and figure 22. half-wave sensing allows low-power dissipation in the sensing resistor, while full-wave sensing has less noise in the sensing signal.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 11 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter figure 21. half-wave sensing figure 22. full-wave sensing 3.1 pulse-by-pulse current limit : in normal operation, the duty cycle of the low-side mosfet is determined by comparing the internal triangular signal with the feedback voltage. however, the low-side mosfet is forced to turn off when the current sense pin voltage reaches -0.58v. this operati on limits the drain current below a pre-determined level to avoid the destruction of the mosfets. 3.2 abnormal over-current protection (aocp) : if one of the secondary rectifier diodes is short-circuited, large current with extremely high di/dt can flow through the mosfet before ocp or olp is triggered. aocp is triggered with a very short shutdown delay time when the sensed voltage drops below -0.9v. this protection is latch mode and reset only when lv cc is pulled below 5v. 3.3 overload protection (olp) : overload is defined as the load current exceeding its nominal level due to an unexpected abnormal event. in this situation, a protection circuit should trigger to protect the power supply. however, even when the power supply is in the normal condition, the olp circuit can be triggered during the load transition. to avoid this undesired operation, the olp circuit is designed to tr igger only after a specified time to determine whether it is a transient situation or a true overload situation. because of the pulse-by-pulse current limit capability, the maximum peak current through the mosfet is limited; and, therefore, the maximum input power is restricted with a given input voltage. if the output consumes more than this maximum power, the output voltage (v o ) decreases below the nominal voltage. this reduces the current through the opto-coupler diode, which also reduces the opto-coupler transistor current, increasing the feedback voltage (v fb ). if v fb exceeds 3v, d1, which is illustrated in figure 19, is blocked and the olp current source starts to charge c b slowly, as shown in figure 23. in this condition, v fb continues increasing until it reaches 7v, then the switching operation is terminated, as shown in figure 23. the delay time for shutdown is the time required to charge c b from 3v to 7v with 5a, as given by: a c v v t b delay 5 ) 3 7 ( = - (2) a 30 ~ 50ms delay time is typical for most applications. v fb t 3v 7v overload protection t delay t 1 t 2 i ds vc i lim v o figure 23. overload protection 3.4 over-voltage protection (ovp) : when the lv cc reaches 23v, ovp is triggered. this protection is enabled when using an auxiliary winding of the transformer to supply lv cc to fps. 3.5 thermal shutdown (tsd) : the mosfets and the control ic are built in one package. this allows the control ic to detect the abnormal over-temperature of the mosfet. if the temperature exceeds approximately 130 c, the thermal shutdown triggers. 4. soft-start : at startup, the duty cycle starts increasing slowly to establish the co rrect working conditions for transformers, inductors, and capacitors. the voltage on the output capacitors is progressively increased to smoothly establish the required output voltage. soft-start time is internally implemented for 15ms (when the operating frequency is set to 100khz.) in addition, to help the soft-start operation, a capacitor and a resistor would be connected on the r t pin externally, as shown in figure 24. before the power supply is powered on, the capacitor c ss remains fully discharged. after power-on, c ss becomes charged progressively by the current
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 12 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter through the r t pin, which determines the operating frequency. the current through the r t pin is inversely proportional to the total impedance of the connected resistors. the total impedance at startup is lower than that of the normal operation because r ss is added on r set in parallel, which means the operating frequency decreases continuously fr om higher to nominal. eventually c ss is fully charged to the r t pin voltage and the operating frequency is determined by r set only. during the charging time of c ss , the operating frequency is higher than during normal operation. in asymmetric half-bridge converters, a sw itching period contains powering and commutation periods. the energy cannot be transferred to the output side during commutation period. since the dc link voltage applied to the v dl pin and the leakage inductance of the main transformer are fixed, the powering period ov er the switching period is shorter in high switching frequencies. as c ss is charged, the switching frequency decreases and the powering period over the switching period increases as well. it is helpful to start smps softly with the internal soft-start time together. figure 24. external soft-start circuit 5. startup: due to the imbalance of the turn-off resistance between the high- and low-side mosfets, the voltage across the dc blocking capacitor cannot be predicted at startup. additionally, the high-side mosfet starts with a large duty cycle since the duty cycle of the low-side mosfet increases step-by-step during soft- start time. therefore, in the case where high voltage is already charged in the dc bl ocking capacitor due to the higher turn-off resistance of the high-side mosfet before startup, a large primary current could flow through the high-side mosfet during turn-on time after startup. for the high-side mosfet, a long duty cycle and high applied voltage make an excessive primary current. when the high-side mosfet turns off, the primary current flows back to the dc link capacitor through the body diode of the low-side mosfet. it keeps the same status even after turning on and off the low-side mosfet. when the high-side mosfet turns on again, a huge current can flow from the dc link capacitor through the channel of the high-side mosfet and body diode of the low-side one due to the reverse recovery. it may induce unexpected noise into cs pin. to avoid this issue, the voltage across the dc blocking capacitor must be low enough. in general, two resistors with several mhz can be added on the drain-to-source terminals of each mosfet to divide the dc link voltage. 6. burst operation : to minimize power dissipation in standby mode, the FSFA2100 enters burst-mode operation. as the load decreases, the feedback voltage decreases. as shown in figure 25, the device automatically enters burst mode when the feedback voltage drops below v bl (1.3v). at this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. this causes the feedback voltage to rise. once it passes v bh (1.5v), switching resumes. the feedback voltage then falls and the process repeats. burst-mode operation alternately enables and disables switching of the mosfets, thereby reducing switching loss in standby mode. v fb v ds 1.3v 1.5v i ds v o vo set t switching stop t 1 switching stop t 2 t 3 t 4 figure 25. burst-mode operation
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 13 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter typical application circuit (asymme tric pwm half-bridge converter) application fps? device input voltage range rated output power output voltage (rated current) lcd tv FSFA2100 400v 200w 25v-8a features ? high efficiency ( >93% at 400v in input) ? reduced emi noise through zero-voltage-switching (zvs) ? enhanced system reliability with various protection functions ? internal soft-start (15ms) figure 26. typical application circuit
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 14 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter typical application circuit (continued) ? core: eer3542 (ae=107 mm 2 ) ? bobbin: eer3542 (horizontal) eer3542 n p 1 89 1 2 16 n s1 1 3 n s2 figure 27. core and winding pin(s f) wire turns winding method n p 8 1 0.12 30 (litz wire) 50 solenoid winding n s1 16 13 0.1 100 (litz wire) 8 solenoid winding n s2 12 9 0.1 100 (litz wire) 8 solenoid winding pin specification remark inductance 1 8 630 h 5% 100khz, 1v leakage 1 8 45 h 10% short one of the secondary windings
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 15 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter physical dimensions sipmodaa09reva figure 28. 9-sip package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com FSFA2100 ? rev. 1.0.0 16 FSFA2100 ? fairchild power switch (fps?) for half-bridge pwm converter

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